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freescale semiconductor data sheet: technical data document number: mcf51mm256 rev. 4, 10/2010 ? freescale semiconductor, inc., 2009-2010. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. an energy-efficient solution from freescale 32-bit coldfire v1 central processor unit (cpu) ? up to 50.33-mhz coldfire cpu above 2.4 v and 40 mhz cpu above 2.1 v and 20 mhz cpu above 1.8 v across temperature range of -40c to 105c. ? coldfire instruction set revision c (isa_c). ? 32-bit multiply and accumulate (mac) supports signed or unsigned integer or signed fractional inputs. on-chip memory ? 256 k flash comprised of two independent 128 k flash arrays; read/program/erase over full operating voltage and temperature; allows interrupt processing while programming. ? 32 kbytes system random-access memory (ram). ? security circuitry to prevent unauthorized access to ram and flash contents. power-saving modes ? two ultra-low power stop modes. peripheral clock enable register can disable clocks to unused modules to reduce currents. ? time of day (tod) ? ultra low-power 1/4 sec counter with up to 64s timeout. ? ultra-low power external oscillator that can be used in stop modes to provide accurate clock source to the tod. 6 usec typical wake up time from stop3 mode. clock source options ? oscillator (xosc1) ? loop-control pierce oscillator; 32.768 khz crystal or ceramic resonator dedicated for tod operation. ? oscillator (xosc2) for high frequency crystal input for mcg reference to be used for system clock and usb operations. ? multipurpose clock generator (mcg) ? pll and fll; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports cpu frequencies from 4 khz to 50 mhz. system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock. ? low-voltage detection with reset or interrupt; selectable trip points; separate low voltage warning with optional interrupt; selectable trip points. ? illegal opcode and illegal address detection with reset. ? flash block protection for each array to prevent accidental write/erasure. ? hardware crc to support fast cyclic redundancy checks. development support ? integrated coldfire debug_rev_b+ interface with single wire bdm connection supports same electrical interface used by the s08 family debug modules. ? real-time debug with 6 hardware breakpoints (4 pc, 1 address and 1 data). ? on-chip trace buffer provides programmable start/stop recording conditions. peripherals ? usb ? dual-role usb on-the-go (otg) device, supports usb in either device, host or otg configuration. on-chip transceiver and 3.3v regulator help save system cost, fully compliant with usb specification 2.0. allows control, bulk, interrupt and isochronous transfers. ? scix ? two serial communications interfaces with optional 13-bit break; option to connect rx input to pracmp output on sci1 and sci2; high current drive on tx on sci1 and sci2; wake-up from stop3 on rx edge. ? spi1 ? serial peripheral interface with 64-bit fifo buffer; 16-bit or 8-bit data transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting. ? spi2 ? serial peripheral interface with full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting. ? iic ? up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing. ? cmt ? carrier modulator timer for remote control communications. carrier generator, modulator and driver for dedicated infrared out (iro). can be used as an output compare timer. ? tpm x ? two 4-channel timer/pwm module; selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel; external clock input/pulse accumulator. ? mini-flexbus ? multi-function external bus interface with user programmable chip selects and the option to multiplex address and data lines. ? pracmp ? analog comparator with selectable interrupt; compare option to programmable internal reference voltage; operation in stop3. measurement engine ? adc16 ? 16-bit successive approximation adc with up to 4 dedicated differential channels and 8 single-ended channels; range compare function; 1.7 mv/ ? c temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 v to 1.8 v, configurable hardware trigger for 8 channel select and result registers. ? pdb ? programmable delay block with 16-bit counter and modulus and prescale to set reference clock to bus divided by 1 to bus divided by 2048; 8 trigger outputs for adc module provides periodic coordination of adc sampling sequence with sequence completion interrupt; back-to-back mode and timed mode. ? dac ? 12-bit resolution; 16-word data buffers with configurable watermark. ? opampx ? 2 flexible operational amplifiers configurable for general operations; low offset and temperature drift. ? triampx ? 2 trans-impedance amplifiers dedicated for converting current inputs into voltages. input/output ? up to 68 gpios and 1 output-only pin. ? voltage reference output (vrefo). ? dedicated infrared output pinwith high current sink capability. ? up to 16 kbi pins with selectable polarity. ? up to 16 pins of rapid general purpose i/o. mcf51mm256/128 the mcf51mm256 series devices are members of the low-cost, low-power, high-performance coldfire ? v1 family of 32-bit microcontrollers (mcus) designed for handheld metering devices. not all features are available in all devices or packages; see ta b l e 2 for a comparison of features by device. 80-lqfp 12mm x 12mm 81-bga 10mm x 10mm 100-lqfp 14mm x 14mm 104-bga 10mm x 10mm document number: mcf51mm256 rev. 4, 10/2010 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
freescale semiconductor 2 table of contents list of topics 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 pinouts and pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1 104-pin mapbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 100-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3 81-pin mapbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.4 80-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .15 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .16 3.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .17 3.4 esd protection characteristics. . . . . . . . . . . . . . . . . . .18 3.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.6 supply current characteristics . . . . . . . . . . . . . . . . . . .23 3.7 pracmp electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.8 12-bit dac electricals. . . . . . . . . . . . . . . . . . . . . . . . . .27 3.9 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.10 mcg and external oscillator (xosc) characteristics .37 3.11 mini-flexbus timing specifications . . . . . . . . . . . . . . .39 3.12 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.12.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.12.2 tpm timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.13 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.14 flash specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.15 usb electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.16 vref electrical specifications . . . . . . . . . . . . . . . . . . .50 3.17 triamp electrical parameters . . . . . . . . . . . . . . . . . . .52 3.18 opamp electrical parameters . . . . . . . . . . . . . . . . . . .53 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.1 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3 mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . .56 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 list of figures figure 1. mcf51mm256/128 block diagram . . . . . . . . . . . . . . . . 4 figure 2. 104-pin mapbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. 100-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. 81-pin mapbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. 80-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. stop idd versus temperature. . . . . . . . . . . . . . . . . . . 26 figure 7. offset at half scale vs temperature . . . . . . . . . . . . . . 29 figure 8. adc input impedance equivalency diagram . . . . . . . 31 figure 9. mini-flexbus read timing . . . . . . . . . . . . . . . . . . . . . 40 figure 10.mini-flexbus write timing . . . . . . . . . . . . . . . . . . . . 41 figure 11.reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12.irq/kbipx timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 13.timer external clock . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 14.timer input capture pulse . . . . . . . . . . . . . . . . . . . . . 44 figure 15.spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . 46 figure 16.spi master timing (cpha = 1) . . . . . . . . . . . . . . . . . 46 figure 17.spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . 47 figure 18.spi slave timing (cpha = 1) . . . . . . . . . . . . . . . . . . 47 figure 19.typical vref output vs. temperature . . . . . . . . . . . . 51 figure 20.typical vref output vs. v dd . . . . . . . . . . . . . . . . . . . 51 list of tables table 1. mcf51mm256/128 features by mcu and package . . 3 table 2. mcf51mm256/128 functional units . . . . . . . . . . . . . . . 5 table 3. package pin assignments . . . . . . . . . . . . . . . . . . . . . . 11 table 4. parameter classifications . . . . . . . . . . . . . . . . . . . . . . 15 table 5. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . 16 table 6. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. esd and latch-up test conditions . . . . . . . . . . . . . . . 18 table 8. esd and latch-up protection characteristics. . . . . . . 18 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10.supply current characteristics . . . . . . . . . . . . . . . . . . 23 table 11.typical stop mode adders. . . . . . . . . . . . . . . . . . . . . . 25 table 12.pracmp electrical specifications . . . . . . . . . . . . . . . 27 table 13.dac 12lv operating requirements . . . . . . . . . . . . . . 27 table 14.dac 12-bit operating behaviors . . . . . . . . . . . . . . . . . 27 table 15.16-bit adc operating conditions . . . . . . . . . . . . . . . . 29 table 16.16-bit sar adc charac teristics full operating range (vrefh = v dda , > 1.8, vrefl = vssa ? 8 mhz, ?40 to 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 17.16-bit sar adc characteristics full operating range (vrefh = vdda, ? 2.7 v, vrefl = vssa, f adack ? 4 mhz, adhsc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18.mcg (temperature range = ?40 to 105c ambient) . 37 table 19.xosc (temperature range = ?40 to 105c ambient) 38 table 20.mini-flexbus ac timing specifications . . . . . . . . . . . . 40 table 21.control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 22.tpm input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23.spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24.flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 25.internal usb 3.3 v voltage regulator characteristics 49 table 26.vref electrical specifications . . . . . . . . . . . . . . . . . 50 table 27.vref limited range operating behaviors . . . . . . . . . 50 table 28.triamp characteristics 1.8?3.6 v, ?40c~105c . . . 52 table 29.opamp characteristics 1.8?3.6 v. . . . . . . . . . . . . . . . 53 table 30.orderable part number summary. . . . . . . . . . . . . . . . 55 table 31.package descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 32.revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
features freescale semiconductor 3 1features the following table provides a cro ss-comparison of the features of the mcf51mm256/128 according to package. table 1. mcf51mm256/128 features by mcu and package feature mcf51mm256 mcf51mm128 flash size (bytes) 262144 131072 ram size (bytes) 32k 32k pin quantity 104 100 81 80 81 80 programmable analog comparator (pracmp) yes yes yes yes yes yes debug module (dbg) yes yes yes yes yes yes multipurpose clock generator (mcg) yes yes yes yes yes yes inter-integrated communication (iic) yes yes yes yes yes yes interrupt request pin (irq) yes yes yes yes yes yes keyboard interrupt (kbi) 16 16 16 16 16 16 digital general purpose i/o 1 1 port i/o count does not include blms , bkgd and irq. blms and bkgd are output only, irq is input only. 69 65 48 47 48 47 dedicated analog input pins 14 14 14 14 14 14 power and ground pins 8 8 8 8 8 8 time of day (tod) yes yes yes yes yes yes serial communications (sci1) yes yes yes yes yes yes serial communications (sci2) yes yes yes yes yes yes serial peripheral interface (spi1(fifo)) yes yes yes yes yes yes serial peripheral interface(spi2) yes yes yes yes yes yes carrier modulator timer pin (iro) yes yes yes yes yes yes tpm input clock pin (tpmclk) yes yes yes yes yes yes tpm1 channels 4 4 4 4 4 4 tpm2 channels 4 4 4 4 4 4 xosc1 yes yes yes yes yes yes xosc2 yes yes yes yes yes yes usb on-the-go yes yes yes yes yes yes mini-flexbus yes yes data 2 2 the 80/81 pin packages contain the mini-fle xbus data pins to support an 8-bit data bus interface to external peripherals. data 2 data 2 data 2 rapid gpio 16 16 9 9 9 9 measurement engine programmable delay block (pdb) yes yes yes yes yes yes 16-bit sar adc differential channels 3 3 each differential channel is comprised of 2 pin inputs. 444444 16-bit sar adc single-ended channels 8 8 8 8 8 8 dac ouput pin (daco) yes yes yes yes yes yes voltage reference output pin (vrefo) yes yes yes yes yes yes general purpose operational amplifier (opamp) yes yes yes yes yes yes trans-impedance amplifier (triamp) yes yes yes yes yes yes freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
features freescale semiconductor 4 figure 1. mcf51mm256/128 block diagram freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
features freescale semiconductor 5 the following table describes the f unctional units of the mcf51mm256/128. table 2. mcf51mm256/128 functional units unit function measurement engine dac (digital to analog converter) ? used to output voltage levels. 16-bit sar adc (analog-to-digital converter) ? measures analog voltages at up to 16 bits of resolution. the adc has up to four differential and 8 single-ended inputs. opamp ? general purpose op amp used for signal filtering or amplification. triamp ?- transimpedance amplif ier optimized for converting small currents into voltages. measurement engine pdb ? the measurement engine pdb is used to precisely trigger the dac and the adc modules to complete sensor biasing and measuring. mini-flexbus provides expansion capability for off-chip memory and peripherals. usb on-the-go supports the usb on-the-go dual-role controller. cmt (carrier modulator timer) infrared output used for the remote controller operation. mcg (multipurpose clock generator) provides clocking options for the device, including a phase-locked loop (pll) and frequency-locked loop (fll) for multiplying slower reference clock sources. bdm (background debug module) provides single pin debugging interface (part of the v1 coldfire core). cf1 core (v1 coldfire core) executes programs and interrupt handlers. pracmp analog comparators for comparing external analog signals against each other, or a variety of reference levels. cop (computer operating properly) software watchdog. irq (interrupt request) single-pin high-priority interrupt (part of the v1 coldfire core). crc (cyclic redundancy check) high-speed crc calculation. dbg (debug) provides debugging and emulation capabilities (part of the v1 coldfire. core) flash (flash memory) provides storage for program code, constants, and variables. iic (inter-integrated circuits) supports standar d iic communications protocol and smbus. intc (interrupt controller) controls and prioritizes all device interrupts. kbi1 & kbi2 keyboard interfaces 1 and 2. lvd (low-voltage detect) provides an interrupt to thecoldfire v1 core in the event that the supply voltage drops below a critical value. the lvd can also be programmed to reset the device upon a low voltage event. vref (voltage reference) the voltage reference outpu t is available for both on- and off-chip use. ram (random-access memory) provide s stack and variable storage. rgpio (rapid general-purpose input/output) allows for i/o port access at cpu clock speeds. rgpio is used to implement gpio functionality. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
features freescale semiconductor 6 sci1, sci2 (serial communications interfaces) serial communications uarts capable of supporting rs-232 and lin protocols. sim (system integration unit) spi1 (fifo), spi2 (serial peripheral interfaces) spi1 and spi2 provide standard master /slave capability. spi contains a fifo buffer in order to increase the throughput for this peripheral. tpm1, tpm2 (timer/pwm module) timer/pwm module can be used for a variety of generic timer operations as well as pulse-width modulation. vreg (voltage regulator) controls power management across the device. xosc1 and xosc2 (crystal oscillators) these devices incorporate redundant crystal oscillators. one is intended primarily for use by the to d, and the other by the cpu and other peripherals. table 2. mcf51mm256/128 functional units (continued) unit function freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 7 2 pinouts and pin assignments 2.1 104-pin mapbga the following figure shows the 104-pin mapbga pinout configuration. 1234567891011 a ptf6 ptf7 usb_dp usb_dm vusb33 ptf4 ptf3 fb_ad12 ptj7 ptj5 ptj4 a b ptg0 pta0 ptg3 vbus ptf5 ptj6 pth0 pte5 ptf0 ptf1 ptf2 b c iro ptg4 pta6 ptg2 ptg6 ptg5 ptg7 pth1 pte4 pte6 pte7 c d pta5 pta4 ptb1 vdd1 vdd2 vdd3 pta1 pte3 pte2 d e vssa pta7 ptb0 pta2 ptj3 pte1 e f vrefl inp1- inp2- ptg1 ptc7 ptj2 ptj0 ptj1 f g triout1 out1 out2 ptd5 ptd7 pte0 g h vinp1 vinn1 pta3 vss1 vss2 vss3 ptd4 ptd3 ptd2 h j dadp0 dadm0 pth7 pth6 pth4 pth3 pth2 ptd6 ptc2 ptc0 ptc1 j k vinp2 vinn2 dadp1 pth5 ptb6 ptb7 ptc3 ptd1 ptc4 ptc5 ptc6 k l triout2 daco dadm1 vrefo vrefh vdda ptb3 ptb2 ptd0 ptb5 ptb4 l 1234567891011 figure 2. 104-pin mapbga freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 8 2.2 100-pin lqfp the following figure shows the 100-pin lqfp pinout configuration. figure 3. 100-pin lqfp ptg0/spsck1 ptf7/miso1 ptf6/mosi1 vdd1 vss1 vbus usb_dp usb_dm vusb33 ptf5/kbi2p7/fb_d3/fb_ad9 ptf4/sda/fb_d4/fb_ad10 ptf3/scl/fb_d5/fb_ad11 fb_ad12 ptj7/fb_ad13 ptj6/fb_ad14 ptj4/rgpiop15/fb_ad16 ptf2/tx2/usb_dm_down/tpm2ch0 ptf1/rx2/usb_dp_down/tpm2ch1 ptf0/usb_id/tpm2ch2 pte7/usb_vbusvld/tpm2ch3 pte6/fb_rw /usb_sessend/rx2 pte5/fb_d7/usb_sessvld/tx2 vdd3 vss3 ptj5/fb_ad15 ptc2/kbi1p5/spsck2/adp6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pta0/fb_d2/ss1 iro ptg5/fb_rw ptg6/fb_ad19 ptg7/fb_ad18 pth0/fb_oe pta1/kbi1p0/tx1/fb_d1 pta2/kbi1p1/rx1/adp4 pta3/kbi1p2/fb_d6/adp5 pta5 pta6 ptb0 ptb1/blms vssa vrefl 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pte3/kbi2p6/fb_ad8 pte2/kbi2p5/rgpiop14/fb_ad7 pte1/kbi2p4/rgpiop13/fb_ad6 ptj3/rgpiop12/fb_ad5 ptj2/fb_ad4 ptj1/fb_ad3 ptj0/fb_ad2 pte0/kbi2p3/fb_ale/fb_cs1 ptd7/usb_pullup(d+)/rx1 ptd6/usb_altclk/tx1 ptd5/scl/rgpiop11/tpm1ch3 ptd4/sda/rgpiop10/tpm1ch2 ptd3/usb_pullup(d+)/rgpiop9/tpm1ch1 ptd2/usb_altclk/rgpiop8/tpm1ch0 ptd1/cmpp2/reset ptd0/bkgd/ms ptc7/kbi2p2/clkout/adp11 ptc6/kbi2p1/pracmpo/adp10 ptc5/kbi2p0/cmpp1/adp9 ptc4/kbi1p7/cmpp0/adp8 ptc1/miso2/fb_d0/fb_ad1 ptc0/mosi2/fb_oe /fb_cs0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 daco dadp0 dadm0 vrefo dadp1 dadm1 vrefh vdda vss2 ptb2/extal1 ptb3/xtal1 vdd2 ptb4/extal2 ptb5/xtal2 ptb6/kbi1p3/rgpiop0/fb_ad17 ptb7/kbi1p4/rgpiop1/fb_ad0 pth2/rgpiop2/fb_d7 pth3/rgpiop3/fb_d6 pth4/rgpiop4/fb_d5 pth5/rgpiop5/fb_d4 pth6/rgpiop6/fb_d3 pth7/rgpiop7/fb_d2 pth1/fb_d0 ptc3/kbi1p6/ss2 /adp7 pte4/cmpp3/tpmclk/irq pta4/inp1+ pta7/inp2+ inp1- out1 triout1/dadp2- vinp1 vinn1/dadm2 inp2- out2 triout2/dadp3 vinp2 vinn2/dadm3 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 9 2.3 81-pin mapbga the following figure shows the 81-pin mapbga pinout configuration. 123456789 a iro ptg0 ptf6 usb_dp vbus vusb33 ptf4 ptf3 pte4 a b ptf7 pta0 ptg1 usb_dm pt f5 pte7 ptf1 ptf0 pte3 b c pta4 pta5 pta6 pta1 ptf2 pte6 pte5 pte2 pte1 c d i n p 1 - p ta 7 p t b 0 p t b 1 p ta 2 p ta 3 p t d 5 p t d 7 p t e 0 d e out1 vinn1 out2 vdd2 vdd3 vdd1 ptd2 ptd3 ptd6 e f vinp1 triout1 inp2- vss2 vss3 vss1 ptb7 ptc7 ptd4 f g dadp0 daco triout2 vinn2 vrefo ptb6 ptc0 ptc1 ptc2 g h dadm0 dadm1 dadp1 vinp2 ptc3 ptc4 ptd0 ptc5 ptc6 h j vssa vrefl vrefh vdda ptb2 ptb3 ptd1 ptb4 ptb5 j 123456789 figure 4. 81-pin mapbga freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 10 2.4 80-pin lqfp the following figure shows the 80-pin lqfp pinout configuration. figure 5. 80-pin lqfp pta0/fb_d2/ss1 iro pta1/kbi1p0/tx1/fb_d1 pta2/kbi1p1/rx1/adp4 pta3/kbi1p2/fb_d6/adp5 pta5 pta6 ptb0 ptb1/blms vssa vrefl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 daco dadp0 dadm0 vrefo dadp1 dadm1 vrefh vdda vss2 ptb2/extal1 ptb3/xtal1 vdd2 ptb4/extal2 ptb5/xtal2 ptb6/kbi1p3/rgpiop0/fb_ad17 ptb7/kbi1p4/rgpiop1/fb_ad0 ptc0/mosi2/fb_oe /fb_cs0 pte3/kbi2p6/fb_ad8 pte2/kbi2p5/rgpiop14/fb_ad7 pte1/kbi2p4/rgpiop13/fb_ad6 pte0/kbi2p3/fb_ale/fb_cs1 ptd7/usb_pullup(d+)/rx1 ptd6/usb_altclk/tx1 ptd5/scl/rgpiop11/tpm1ch3 ptd4/sda/rgpiop10/tpm1ch2 ptd3/usb_pullup(d+)/rgpiop9/tpm1ch1 ptd2/usb_altclk/rgpiop8/tpm1ch0 ptd1/cmpp2/reset ptd0/bkgd/ms ptc7/kbi2p2/clkout/adp11 ptc6/kbi2p1/pracmpo/adp10 ptc5/kbi2p0/cmpp1/adp9 ptc4/kbi1p7/cmpp0/adp8 ptc3/kbi1p6/ss2 /adp7 ptc2/kbi1p5/spsck2/adp6 ptc1/miso2/fb_d0/fb_ad1 ptg0/spsck1 ptf7/miso1 ptf6/mosi1 vdd1 vss1 vbus usb_dp usb_dm vusb33 ptf5/kbi2p7/fb_d3/fb_ad9 ptf4/sda/fb_d4/fb_ad10 ptf3/scl/fb_d5/fb_ad11 ptf2/tx2/usb_dm_down/tpm2ch0 ptf1/rx2/usb_dp_down/tpm2ch1 ptf0/usb_id/tpm2ch2 pte7/usb_vbusvld/tpm2ch3 pte6/fb_rw /usb_sessend/rx2 pte5/fb_d7/usb_sessvld/tx2 vdd3 vss3 80-pin lqfp pte4/cmpp3/tpmclk/irq pta4/inp1+ pta7/inp2+ inp1- out1 triout1/dadp2- vinp1 vinn1dadm2 inp2- out2 triout2/dadp3 vinp2 vinn2/dadm3 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 11 2.5 pin assignments table 3. package pin assignments package default function alternate 1 alternate 2 alternate 3 composite pin name 104 mapbga 100 lqfp 81 mapbga 80 lqfp b2 1 b2 1 pta0 fb_d2 ss1 ? pta0/fb_d2/ss1 c1 2 a1 2 iro ? ? ? iro c6 3 ? ? ptg5 fb_rw ? ? ptg5/fb_rw c5 4 ? ? ptg6 fb_ad19 ? ? ptg6/fb_ad19 c7 5 ? ? ptg7 fb_ad18 ? ? ptg7/fb_ad18 b7 6 ? ? pth0 fb_o e ? ? pth0/fb_oe c8 7 ? ? pth1 fb_d0 ? ? pth1/fb_d0 d9 8 c4 3 pta1 kbi1p0 tx1 fb_d1 pta1/kbi1p0/tx1/fb_d1 e9 9 d5 4 pta2 kbi1p1 rx1 adp4 pta2/kbi1p1/rx1/adp4 h3 10 d6 5 pta3 kbi1p2 fb_d6 adp5 pta3/kbi1p2/fb_d6/adp5 d2 11 c1 6 pta4 inp1+ ? ? pta4/inp1+ d1 12 c2 7 pta5 ? ? ? pta5 c3 13 c3 8 pta6 ? ? ? pta6 e2 14 d2 9 pta7 inp2+ ? ? pta7/inp2+ e3 15 d3 10 ptb0 ? ? ? ptb0 d3 16 d4 11 ptb1 blms ? ? ptb1/blms e1 17 j1 12 vssa ? ? ? vssa f1 18 j2 13 vrefl ? ? ? vrefl f2 19 d1 14 inp1- ? ? ? inp1- g2 20 e1 15 out1 ? ? ? out1 g1 21 f2 16 dadp2 triout1 ? ? dadp2/triout1 h1 22 f1 17 vinp1 ? ? ? vinp1 h2 23 e2 18 dadm2 vinn1 ? ? dadm2/vinn1 f3 24 f3 19 inp2- ? ? ? inp2- g3 25 e3 20 out2 ? ? ? out2 l2 26 g2 21 daco ? ? ? daco l1 27 g3 22 dadp3 triout2 ? ? dadp3/triout2 k1 28 h4 23 vinp2 ? ? ? vinp2 k2 29 g4 24 dadm3 vinn2 ? ? dadm3/vinn2 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 12 j1 30 g1 25 dadp0 ? ? ? dadp0 j2 31 h1 26 dadm0 ? ? ? dadm0 l4 32 g5 27 vrefo ? ? ? vrefo k3 33 h3 28 dadp1 ? ? ? dadp1 l3 34 h2 29 dadm1 ? ? ? dadm1 l5 35 j3 30 vrefh ? ? ? vrefh l6 36 j4 31 vdda ? ? ? vdda h6 37 f4 32 vss2 ? ? ? vss2 l8 38 j5 33 ptb2 extal1 ? ? ptb2/extal1 l7 39 j6 34 ptb3 xtal1 ? ? ptb3/xtal1 d6 40 e4 35 vdd2 ? ? ? vdd2 l11 41 j8 36 ptb4 extal2 ? ? ptb4/extal2 l10 42 j9 37 ptb5 xtal2 ? ? ptb5/xtal2 k5 43 g6 38 ptb6 kbi1p3 rgpiop0 fb_ad1 7 ptb6/kbi1p3/rgpiop0/fb_ad17 k6 44 f7 39 ptb7 kbi1p4 rgpiop1 fb_ad0 ptb7/kbi1p4/rgpiop1/fb_ad0 j7 45 ? ? pth2 rgpiop2 fb_d7 ? pth2/rgpiop2/fb_d7 j6 46 ? ? pth3 rgpiop3 fb_d6 ? pth3/rgpiop3/fb_d6 j5 47 ? ? pth4 rgpiop4 fb_d5 ? pth4/rgpiop4/fb_d5 k4 48 ? ? pth5 rgpiop5 fb_d4 ? pth5/rgpiop5/fb_d4 j4 49 ? ? pth6 rgpiop6 fb_d3 ? pth6/rgpiop6/fb_d3 j3 50 ? ? pth7 rgpiop7 fb_d2 ? pth7/rgpiop7/fb_d2 j10 51 g7 40 ptc0 mosi2 fb_o e fb_cs0 ptc0/mosi2/fb_oe /fb_cs0 j11 52 g8 41 ptc1 miso2 fb_d0 fb_ad1 ptc1/miso2/fb_d0/fb_ad1 j9 53 g9 42 ptc2 kbi1p5 spsck2 adp6 ptc2/kbi1p5/spsck2/adp6 k7 54 h5 43 ptc3 kbi1p6 ss2 adp7 ptc3/kbi1p6/ss2 /adp7 k9 55 h6 44 ptc4 kbi1p7 cmpp0 adp8 ptc4/kbi1p7/cmpp0/adp8 k10 56 h8 45 ptc5 kbi2p0 cmpp1 adp9 ptc5/kbi2p0/cmpp1/adp9 k11 57 h9 46 ptc6 kbi2p1 pracmpo adp10 ptc6/kbi2p1/pracmpo/adp10 f8 58 f8 47 ptc7 kbi2p2 clkout adp11 ptc7/kbi2p2/clkout/adp11 l9 59 h7 48 ptd0 bkgd ms ? ptd0/bkgd/ms k8 60 j7 49 ptd1 cmpp2 reset ? ptd1/cmpp2/reset table 3. package pin assignments (continued) package default function alternate 1 alternate 2 alternate 3 composite pin name 104 mapbga 100 lqfp 81 mapbga 80 lqfp freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 13 h11 61 e7 50 ptd2 usb_altclk rgpiop8 tpm1c h0 ptd2/usb_altclk/rgpiop8/tpm1ch0 h10 62 e8 51 ptd3 usb_pullup (d+) rgpiop9 tpm1ch1 ptd3/usb_p ullup(d+)/rgpiop9/tpm1ch1 h9 63 f9 52 ptd4 sda rgpiop10 tpm1ch2 ptd4/sda/rgpiop10/tpm1ch2 g9 64 d7 53 ptd5 scl rgpiop11 tpm1ch3 ptd5/scl/rgpiop11/tpm1ch3 j8 65 e9 54 ptd6 usb_altclk tx1 ? ptd6/usb_altclk/tx1 g10 66 d8 55 ptd7 usb_pullup (d+) rx1 ? ptd7/usb_pullup(d+) /rx1 g11 67 d9 56 pte0 kbi2p3 fb_ale fb_ cs1 pte0/kbi2p3/fb_ale/fb_cs1 f10 68 ? ? ptj0 fb_ad2 ? ? ptj0/fb_ad2 f11 69 ? ? ptj1 fb_ad3 ? ? ptj1/fb_ad3 f9 70 ? ? ptj2 fb_ad4 ? ? ptj2/fb_ad4 e10 71 ? ? ptj3 rgpiop12 fb_ad5 ? ptj3/rgpiop12/fb_ad5 e11 72 c9 57 pte1 kbi2p4 rgpiop13 fb_ ad6 pte1/kbi2p4/rgpiop13/fb_ad6 d11 73 c8 58 pte2 kbi2p5 rgpiop14 fb_ ad7 pte2/kbi2p5/rgpiop14/fb_ad7 d10 74 b9 59 pte3 kbi2p6 fb_ad8 ? pte3/kbi2p6/fb_ad8 c9 75 a9 60 pte4 cmpp3 tpmclk irq pte4/cmpp3/tpmclk/irq h8 76 f5 61 vss3 ? ? ? vss3 d8 77 e5 62 vdd3 ? ? ? vdd3 b8 78 c7 63 pte5 fb_d7 usb_ sessvld tx2 pte5/fb_d7/usb_sessvld/tx2 c10 79 c6 64 pte6 fb_rw usb_ sessend rx2 pte6/fb_rw /usb_sessend/rx2 c11 80 b6 65 pte7 usb_ vbusvld tpm2ch3 ? pte7/usb_vbusvld/tpm2ch3 b9 81 b8 66 ptf0 usb_id tpm2 ch2 ? ptf0/usb_id/tpm2ch2 b10 82 b7 67 ptf1 rx2 usb_dp_d own tpm2ch1 ptf1/rx2/usb_dp_down/tpm2ch1 b11 83 c5 68 ptf2 tx2 usb_dm_ down tpm2ch0 ptf2/tx2/usb_dm_down/tpm2ch0 a11 84 ? ? ptj4 rgpiop15 fb_ad 16 ? ptj4/rgpiop15/fb_ad16 a10 85 ? ? ptj5 fb_ad15 ? ? ptj5/fb_ad15 b6 86 ? ? ptj6 fb_ad14 ? ? ptj6/fb_ad14 a9 87 ? ? ptj7 fb_ad13 ? ? ptj7/fb_ad13 table 3. package pin assignments (continued) package default function alternate 1 alternate 2 alternate 3 composite pin name 104 mapbga 100 lqfp 81 mapbga 80 lqfp freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
pinouts and pin assignments freescale semiconductor 14 a8 88 ? ? fb_ad12 ? ? ? fb_ad12 a7 89 a8 69 ptf3 scl fb_d5 fb_ad1 1 ptf3/scl/fb_d5/fb_ad11 a6 90 a7 70 ptf4 sda fb_d4 fb_ad10 ptf4/sda/fb_d4/fb_ad10 b5 91 b5 71 ptf5 kbi2p7 fb_d3 fb_ad9 ptf5/kbi2p7/fb_d3/fb_ad9 a5 92 a6 72 vusb33 ? ? ? vusb33 a4 93 b4 73 usb_dm ? ? ? usb_dm a3 94 a4 74 usb_dp ? ? ? usb_dp b4 95 a5 75 vbus ? ? ? vbus h4 96 f6 76 vss1 ? ? ? vss1 d4 97 e6 77 vdd1 ? ? ? vdd1 a1 98 a3 78 ptf6 mosi1 ? ? ptf6/mosi1 a2 99 b1 79 ptf7 miso1 ? ? ptf7/miso1 b1 100 a2 80 ptg0 spsck1 ? ? ptg0/spsck1 f4 ? a1 ? ptg1 usb_ sessend ? ? ptg1/usb_sessend c4 ? ? ? ptg2 usb_dm_ down ? ? ptg2/usb_dm_down b3 ? ? ? ptg3 usb_dp_ down ? ? ptg3/usb_dp_down c2 ? ? ? ptg4 usb_sessvld ? ? ptg4/usb_sessvld table 3. package pin assignments (continued) package default function alternate 1 alternate 2 alternate 3 composite pin name 104 mapbga 100 lqfp 81 mapbga 80 lqfp freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 15 3 electrical characteristics this section contains electrical specification tables and refe rence timing diagrams for the mcf51mm256/128 microcontroller, including detailed information on power considerations, dc/ac electrical characteristics, an d ac timing sp ecifications. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stag e of the product life cycle. these specifications will, however, be met for production silicon. finalized specifications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this data sheet supersede any values found in the module specifications. 3.1 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. table 4. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 16 3.2 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits speci fied in the following table may af fect device reliability or cause permanent damage to the de vice. for functional operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). table 5. absolute maximum ratings # rating symbol value unit 1 supply voltage v dd ?0.3 to +3.8 v 2 maximum current into v dd i dd 120 ma 3 digital input voltage v in ?0.3 to v dd +0.3 v 4 instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value specified. to determine the value of the requi red current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if posit ive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the cl ock rate is very low (which would reduce overall power consumption). i d ? 25 ma 5 storage temperature range t stg ?55 to 150 ?c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 17 3.3 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-deter mined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. ex cept in cases of unusuall y high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in ?c can be obtained from: t j = t a + (p d ? ? ja ) eqn. 1 where: t a = ambient temperature, ? c ? ja = package thermal resist ance, junction-to-ambient, ? c/w p d = p int ?? p i/o p int = i dd ? v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined table 6. thermal characteristics # symbol rating value unit 1t a operating temperature range (packaged): ?c mcf51mm256 ?40 to 105 mcf51mm128 ?40 to 105 2t jmax maximum junction temperature 135 ?c 3 ? ja thermal resistance 1,2,3,4 single-layer board ? 1s 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resi stance, mounting site (board) temperature, ambient temperature, air flow, power dissipati on of other components on the board, and board thermal resistance. 2 junction to ambient natural convection 3 1s ? single layer board, one signal layer 4 2s2p ? four layer board, 2 signal and 2 power layers ?c/w 104-pin mbga 67 100-pin lqfp 53 81-pin mbga 67 80-pin lqfp 53 4 ? ja thermal resistance 1, 2, 3, 4 four-layer board ? 2s2p ?c/w 104-pin mbga 39 100-pin lqfp 41 81-pin mbga 39 80-pin lqfp 39 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 18 for most applications, p i/o ?? p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k ? (t j + 273 ? c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d ? (t a + 273 ? c) + ? ja ? (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.4 esd protection characteristics although damage from static disc harge is much less common on th ese devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with cdf-aec-q00 stress test qu alification for automotive grade integrated circuits. ( http://www.aecouncil.com/ ) this device was qualified to aec-q100 rev e. a device is considered to have failed if, after exposure to esd pulses, the device no longer meets the device specification requireme nts. complete dc parametric and fu nctional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the de vice specification. table 7. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ? storage capacitance c 100 pf number of pulse per pin ? 3 ? machine series resistance r1 0 ? storage capacitance c 200 pf number of pulse per pin ? 3 ? latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table 8. esd and latch-up protection characteristics # rating symbol min max unit c 1 human body model (hbm) v hbm ? 2000 ? v t 2 machine model (mm) v mm ? 200 ? v t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 19 3 charge device model (cdm) v cdm ? 500 ? v t 4 latch-up current at t a = 125 ?ci lat ?? 00 ? ma t table 8. esd and latch-up protection characteristics (continued) freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 20 3.5 dc characteristics this section includes information about power supply requirements, i/o pin characteristics, and power supply current in various operating modes. table 9. dc characteristics num symbol characteristic condition min typ 1 max unit c 1? operating voltage ?1.8 2 ?3.6v? 2v oh output high voltage all i/o pins, low-drive strength v dd ? 1.8 v, i load = ?600 ? a v dd ? 0.5 ? ? v c all i/o pins, high-drive strength v dd ? 2.7 v, i load = ?10 ma v dd ? 0.5 ? ? v p v dd ? 2.3 v, i load = ?6 ma v dd ? 0.5 ? ? v t v dd ? 1.8v, i load = ?3 ma v dd ? 0.5 ? ? v c 3i oht output high current max total i oh for all ports ???1 0 0m ad 4v ol output low voltage all i/o pins, low-drive strength v dd ? 1.8 v, i load = 600 ? a ??0.5vc all i/o pins, high-drive strength v dd ? 2.7 v, i load = 10 ma ??0.5vp v dd ? 2.3 v, i load = 6 ma ??0.5vt v dd ? 1.8 v, i load = 3 ma ??0.5vc 5i olt output low current max total i ol for all ports ???100mad 6v ih input high voltage all digital inputs v dd ? 2.7 v 0.70 x v dd ??vp v dd ?? 1.8 v 0.85 x v dd ??vc freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 21 7v il input low voltage all digital inputs v dd ? 2.7 v ? ? 0.35 x v dd vp v dd ? 1.8 v ? ? 0.30 x v dd vc 8v hys input hysteresis all digital inputs ? 0.06 x v dd ??mvc 9|i in| input leakage current all input only pins (per pin) v in = v dd or v ss ??0.5 ? ap 10 |i oz| hi-z (off-state) leakage current 3 all digital input/output (per pin) v in = v dd or v ss ?0.0030.5 ? ap 11 r pu pull-up resistors all digital inputs, when enabled ? 17.5 ? 52.5 k ? p 12 r pd internal pull-down resistors 4 ? 17.5 ? 52.5 k ? p 13 i ic dc injection current 5, 6, 7 single pin limit v ss > v in > v dd ?0.2 ? 0.2 ma d total mcu limit, includes sum of all stressed pins v ss > v in > v dd ?5 ? 5 ma d 14 c in input capacitance, all pins ? ? ? 8 pf c 15 v ram ram retention voltage ? ? 0.6 1.0 v c 16 v por por re-arm voltage 8 ? 0.9 1.4 1.79 v c 17 t por por re-arm time ? 10 ? ? ? sd 18 v lvd h 9 low-voltage detection threshold ? high range v dd falling ? 2.11 2.16 2.22 v p v dd rising ? 2.16 2.21 2.27 v p 19 v lv d l low-voltage detection threshold ? low range 9 v dd falling ? 1.80 1.82 1.91 v p v dd rising ? 1.86 1.90 1.99 v p table 9. dc characteristics (continued) num symbol characteristic condition min typ 1 max unit c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 22 20 v lvw h low-voltage warning threshold ? high range 9 v dd falling ? 2.36 2.46 2.56 v p v dd rising ? 2.36 2.46 2.56 v p 21 v lvw l low-voltage warning threshold ? low range 9 v dd falling ? 2.11 2.16 2.22 v p v dd rising ? 2.16 2.21 2.27 v p 22 v hys low-voltage inhibit reset/recoverhysteresis 10 ??50?mvc 23 v bg bandgap voltage reference 11 ? 1.110 1.17 1.230 v p 1 typical values are measured at 25 ? c. characterized, not tested 2 as the supply voltage rises, the lvd circuit will hold the mcu in reset until t he supply has risen above v lvdl . 3 does not include analog module pins. dedica ted analog pins should not be pulled to v dd or v ss and should be left floating when not used to reduce current leakage. 4 measured with v in = v dd . 5 all functional non-supply pins are internally clamped to v ss and v dd except ptd1. 6 input must be current limited to the value specified. to deter mine the value of the required cu rrent-limiting resistor, calcula te resistance values for positive and negative clamp vo ltages, then use the larger of the two values. 7 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maxi mum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (w hich would reduce overall power consumption). 8 maximum is highest voltage that por is guaranteed. 9 run at 1 mhz bus frequency 10 low voltage detection and warning limi ts measured at 1 mhz bus frequency. 11 factory trimmed at v dd = 3.0 v, temp = 25 ? c table 9. dc characteristics (continued) num symbol characteristic condition min typ 1 max unit c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 23 3.6 supply current characteristics table 10. supply current characteristics # symbol parameter bus freq v dd (v) typ 1 max unit temp (? c) c 1ri dd run supply current fei mode; all modules on 2 25.165 mhz 34448 ma ?40 to 25 p 25.165 mhz 34448 ma 105 p 20 mhz 3 32.3 ? ma ?40 to 105 t 8 mhz 3 16.4 ? ma ?40 to 105 t 1 mhz 3 2.9 ? ma ?40 to 105 t 2ri dd run supply current fei mode; all modules off 3 25.165 mhz 3 29 29.6 ma ?40 to 105 c 20 mhz 3 25.4 ? ma ?40 to 105 t 8 mhz 3 12.7 ? ma ?40 to 105 t 1 mhz 3 2.4 ? ma ?40 to 105 t 3ri dd run supply current lps=0; all modules off 3 16 khz fbilp 3 232 280 ? a ?40 to 105 t 16 khz fbelp 3 231 296 ? a ?40 to 105 t 4 ri dd run supply current lps=1, all modules off 3 16 khz fbelp 37475 ? a 0 to 70 t 16 khz fbelp 3 74 120 ? a ?40 to 105 t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 24 5 wi dd wait mode supply current fei mode, all modules off 3 25.165 mhz 316.5? ma ?40 to 105 c 20 mhz 3 10.3 ? ma ?40 to 105 t 8 mhz 3 6.6 ? ma ?40 to 105 t 1 mhz 3 1.7 ? ma ?40 to 105 t 6 lpwi dd low-power wait mode supply current 16 khz 3 28 62 a ?40 to 105 t 7 s2i dd stop2 mode supply current 4 n/a 3 0.410 1.00 a ?40 to 25 p n/a 3 3.7 10 a 70 c n/a 3 10 20 a 85 c n/a 3 21 31.5 a 105 p n/a 2 0.410 0.640 a ?40 to 25 c n/a 2 3.4 9 a 70 c n/a 2 9.5 18 a 85 c n/a 2 20 30 a 105 c table 10. supply current characteristics (continued) # symbol parameter bus freq v dd (v) typ 1 max unit temp (? c) c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 25 8 s3i dd stop3 mode supply current 4 no clocks active n/a 3 0.650 1.0 a ?40 to 25 p n/a 3 8.5 18 a 70 c n/a 3 20 28 a 85 c n/a 3 53 63 a 105 p n/a 2 0.400 0.900 a ?40 to 25 c n/a 2 8.2 16 a 70 c n/a 2 18 26 a 85 c n/a 2 47 59 a 105 c 1 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. 2 on = system clock gating control registers tu rn on system clock to the corresponding modules. 3 off = system clock gating control registers turn off system clock to the corresponding modules. 4 all digital pins must be configured to a known state to prevent floating pins from adding curren t. smaller packages may have so me pins that are not bonded out; however, software must still be conf igured to the largest pin package available so that all pins are in a known state. otherwise, floating pins that are not bonded in the smaller packages may result in a higher current draw. note: i/o pins are configured to output low, input-only pins are configured to pull up enabled. iro pin connects to ground. fb_a d12 pin is pullup enabled. triamp x , opamp x , daco, and vrefo pins are at reset state and unconnected. table 11. typical stop mode adders # parameter condition temperature (c) units c ?40 25 70 85 105 1 lpo ? 50 75 100 150 250 na d 2 erefsten range = hgo = 0 600 650 750 850 1000 na d 3irefsten 1 ? ? 73 80 93 125 a t 4tod does not include clock source current 50 75 100 150 250 na d 5lvd 1 lvdse = 1 116 117 126 132 172 a t 6 pracmp 1 not using the bandgap (bgbe = 0) 17 18 24 35 74 a t 7adc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) 190 195 210 220 260 a t table 10. supply current characteristics (continued) # symbol parameter bus freq v dd (v) typ 1 max unit temp (? c) c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 26 figure 6. stop idd versus temperature 8 dac 1 high-power mode; no load on daco 339 345 346 346 360 a t low-power mode 41 43 43 44 50 a t 9 opamp 1 high-power mode 276 350 370 376 390 a t low-power mode 42 49 57 58 68 a t 10 triamp 1 high-power mode 420 432 433 438 478 a t low-power mode 52 52 52 55 60 a t 1 not available in stop2 mode. table 11. typical stop mode adders (continued) # parameter condition temperature (c) units c ?40 25 70 85 105 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 27 3.7 pracmp electricals 3.8 12-bit dac electricals table 12. pracmp electrical specifications # characteristic symbol min typical max unit c 1 supply voltage v pwr 1.8 ? 3.6 v p 2 supply current (active) (prg enabled) i ddact1 ??80 ? ad 3 supply current (active) (prg disabled) i ddact2 ??40 ? ad 4 supply current (acmp and prg all disabled) i dddis ?? 2 nad 5 analog input voltage vain v ss ? 0.3 ? v dd vd 6 analog input offset voltage vaio ? 5 40 mv d 7 analog comparator hysteresis v h 3.0 ? 20.0 mv d 8 analog input leakage current i alkg ?? 1 nad 9 analog comparator initialization delay tainit ? ? 1.0 ? sd 10 programmable reference generator inputs v in2 (v dd25 )1.8 ? 2.75 v d 11 programmable reference generator setup delay t prgst ?1?sd 12 programmable reference generator step size vstep 0.75 1 1.25 lsb d 13 programmable reference generator voltage range vprgout v in /32 ? v in vp table 13. dac 12lv operating requirements # characteristic symbo l min max unit c notes 1 supply voltage v dda 1.8 3.6 v p 2 reference voltage v dacr 1.15 3.6 v c 3 temperature t a ?40 105 c c 4 output load capacitance c l ? 100 p f c a small load capaci- tance (47 p f ) can improve the band- width performance of the dac. 5 output load current i l ?1mac table 14. dac 12-bit operating behaviors # characteristic symbol min typ max unit c notes 1 resolution n 12 ? 12 bit t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 28 2 supply current low-power mode i dda_daclp ?50 100 a t 3 supply current high-power mode i dda_dachp ? 345 500 a t 4 f ull-scale settling time (1 lsb) (0x080 to 0xf7f or 0xf7f to 0x080) low-power mode ts fs lp ? ? 200 s t ?v dda = 3 v or 2.2 v ?v refsel = 1 ? temperature = 25c 5 f ull-scale settling time (1 lsb) (0x080 to 0xf7f or 0xf7f to 0x080) high-power mode ts fs hp ? ? 30 s t ?v dda = 3 v or 2.2 v ?v refsel = 1 ? temperature = 25c 6 code-to-code settling time (1 lsb) (0xbf8 to 0xc08 or 0xc08 to 0xbf8) low-power mode ts c-c lp ?? 5 s t ?v dda = 3 v or 2.2 v ?v refsel = 1 ? temperature = 25c 7 code-to-code settling time (1 lsb) (0xbf8 to 0xc08 or 0xc08 to 0xbf8) high-power mode (3 v at room temperature) ts c-c hp ?1? s t ?v dda = 3 v or 2.2 v ?v refsel = 1 ? temperature = 25c 8 dac output voltage range low (high-power mode, no load, dac set to 0) (3 v at room temperature) v dacoutl ? ? 100 mv t 9 dac output voltage range high (high-power mode, no load, dac set to 0x0fff) v dacouth v dacr -100 ? ?mv t 10 integral non-linearity error inl ? ? 8 lsb t 11 differential non-linearity error vdacr is > 2.4 v dnl ? ? 1 lsb t 12 offset error e o ? 0.4 3 %fsr t calculated by a best fit curve from v ss + 100mv to v refh ?100mv 13 gain error, v refh = v ext = v dd e g ? 0.1 0.5 %fsr t calculated by a best fit curve from v ss + 100mv to v refh ?100mv table 14. dac 12-bit operating behaviors (continued) # characteristic symbol min typ max unit c notes freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 29 figure 7. offset at half scale vs temperature 3.9 adc characteristics 14 power supply rejection ratio v dd ? 2.4 v psrr 60 ?? db t 15 temperature drift of offset voltage (dac set to 0x0800) t co ?? 2mv t see typical drift figure that follows. 16 offset aging coefficient a c ?? 8 v/yr t table 15. 16-bit adc operating conditions # symb characteristic conditions min typ 1 max unit c comment 1v dda supply voltage absolute 1.8 ? 3.6 v d 2 ? v dda delta to v dd (v dd ?v dda ) 2 ?100 0 +100 mv d 3 ? v ssa ground voltage delta to v ss (v ss ?v ssa ) 2 ?100 0 +100 mv d 4v refh ref voltage high 1.15 v dda v dda vd table 14. dac 12-bit operating behaviors (continued) # characteristic symbol min typ max unit c notes freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 30 5v refl ref voltage low v ssa v ssa v ssa vd 6v adin input voltage v refl ?v refh vd 7c adin input capacitance 16-bit modes 8/10/12-bit modes ? 8 4 10 5 pf t 8r adin input resistance ? 2 5 k ? t 9r as analog source resistance external to mcu assumes adlsmp=0 16-bit mode f adck > 8 mhz ??0.5k ? t 4 mhz < f adck < 8 mhz ??1k ? t f adck < 4 mhz ? ? 2 k ? t 13/12-bit mode f adck > 8 mhz ??1k ? t 4 mhz < f adck < 8 mhz ??2k ? t f adck < 4 mhz ? ? 5 k ? t 11/10-bit mode f adck > 8 mhz ??2k ? t 4 mhz < f adck < 8 mhz ??5k ? t f adck < 4 mhz ? ? 10 k ? t 9/8-bit mode f adck > 8 mhz ??5k ? t f adck < 8 mhz ? ? 10 k ? t 10 f adck adc conversion clock frequency adlpc=0, adhsc=1 1.0 ? 8.0 mhz d adlpc=0, adhsc=0 1.0 ? 5.0 mhz d adlpc=1, adhsc=0 1.0 ? 2.5 mhz d 1 typical values assume v dda = 3.0 v, temp = 25 ? c, f adck =1.0 mhz unless otherwise stated. ty pical values are for reference only and are not tested in production. 2 dc potential difference. table 15. 16-bit adc operati ng conditions (continued) # symb characteristic conditions min typ 1 max unit c comment freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 31 figure 8. adc input impedanc e equivalency diagram + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 32 table 16. 16-bit sar adc characteristics full operating range (v refh = v dda , > 1.8, v refl = v ssa ? 8 mhz, ?40 to 85 c) # characteristic conditions 1 symb min typ 2 max unit c comment supply current adlpc=1, adhsc=0 i ddad ?215 ? ? at adlsmp =0 adco=1 1 adlpc=0, adhsc=0 ? 470 ? adlpc=0, adhsc=1 ? 610 ? 2 supply current stop, reset, module off i ddad ?0.01 ? ? at adc asynchronous clock source adlpc=1, adhsc=0 f adack ?2.4 ? mhz ct adack = 1/f adack 3 adlpc=0, adhsc=0 ? 5.2 ? adlpc=0, adhsc=1 ? 6.2 ? 4 sample time see reference manual for sample times 5 conversion time see reference manual for conversion times 6 to t a l unadjusted error 16-bit differential mode 16-bit single-ended mode tue ? ? ? 16 ? 20 ? 48/ ?40 ? 56/ ?28 lsb 3 t 32x hardware averaging (avge = %1 avgs = %11) 13-bit differential mode 12-bit single-ended mode ? ? ? 1.5 ? 1.75 ? 3.0 ? 3.5 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.7 ? 0.8 ? 1.5 ? 1.5 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 1.0 ? 1.0 t 7 differential non-linearity 16-bit differential mode 16-bit single-ended mode dnl ? ? ? 2.5 ? 2.5 ? 5/?3 +5/?3 lsb 2 t 13-bit differential mode 12-bit single-ended mode ? ? ? 0.7 ? 0.7 ? 1 ? 1 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 0.75 ? 0.75 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 33 8 integral non-linearity 16-bit differential mode 16-bit single-ended mode inl ? ? ? 6.0 ? 10.0 ? 16.0 ? 20.0 lsb 2 t 13-bit differential mode 12-bit single-ended mode ? ? ? 1.0 ? 1.0 ? 2.5 ? 2.5 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 1.0 ? 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.3 ? 0.3 ? 0.5 ? 0.5 t 9 zero-scale error 16-bit differential mode 16-bit single-ended mode e zs ? ? ? 4.0 ? 4.0 +32/ ?24 +24/ ?16 lsb 2 t v adin = v ssa 13-bit differential mode 12-bit single-ended mode ? ? ? 0.7 ? 0.7 ? 2.5 ? 2.0 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.4 ? 0.4 ? 1.0 ? 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t 10 full-scale error 16-bit differential mode 16-bit single-ended mode e fs ? ? +10/0 +14/0 +42/?2 +46/?2 lsb 2 t v adin = v dda 13-bit differential mode 12-bit single-ended mode ? ? ? 1.0 ? 1.0 ? 3.5 ? 3.5 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.4 ? 0.4 ? 1.5 ? 1.5 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t 11 quantization error 16-bit modes e q ? ?1 to 0 ? lsb 2 d < 13-bit modes ? ? ? 0.5 12 effective number of bits 16-bit differential mode avg=32 avg=16 avg=8 avg=4 avg=1 enob 12.8 12.7 12.6 12.5 11.9 14.2 13.8 13.6 13.3 12.5 ? ? ? ? ? bits c f in = f sample /10 0 13 signal to noise plus distortion see enob sinad db table 16. 16-bit sar adc characteristics full operating range (v refh = v dda , > 1.8, v refl = v ssa ? 8 mhz, ?40 to 85 c) (continued) # characteristic conditions 1 symb min typ 2 max unit c comment sinad 6.02 enob ? 1.76 + = freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 34 14 total harmonic distortion 16-bit differential mode avg=32 thd ? ?91.5 ?74.3 db c f in = f sample /10 0 16-bit single-ended mode avg=32 ? ?85.5 ? d 15 spurious free dynamic range 16-bit differential mode avg=32 sfdr 75.0 92.2 ? db c f in = f sample /10 0 16-bit single-ended mode avg=32 ? 86.2 ? d 16 input leakage error all modes e il i in * r as mv d i in = leakage current (refer to dc characteri stics) 17 temp sensor slope ?40 ? c ? 25 ?c m ?1.646 ? mv/ c c 25? c ? 125?c ? 1.769 ? 18 temp sensor voltage 25?c v temp2 5 ?718.2 ? mvc 1 all accuracy numbers assume the adc is calibrated with v refh =v dda 2 typical values assume v dda = 3.0v, temp = 25 ? c, f adck =2.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3 1 lsb = (v refh ? v refl )/2 n table 16. 16-bit sar adc characteristics full operating range (v refh = v dda , > 1.8, v refl = v ssa ? 8 mhz, ?40 to 85 c) (continued) # characteristic conditions 1 symb min typ 2 max unit c comment freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 35 table 17. 16-bit sar adc charac teristics full operating range (v refh = v dda , ? 2.7 v, v refl = v ssa , f adack ? 4 mhz, adhsc = 1) # characteristic conditions 1 symb min typ 2 max unit c comment 1 to t a l unadjusted error 16-bit differential mode 16-bit single-ended mode tue ? ? ? 16 ? 20 ? 24/ ?24 ? 32/?20 lsb 3 t 32x hardware averaging (avge = %1 avgs = %11) 13-bit differential mode 12-bit single-ended mode ? ? ? 1.5 ? 1.75 ? 2.0 ? 2.5 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.7 ? 0.8 ? 1.0 ? 1.25 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 1.0 ? 1.0 t 2 differential non-linearity 16-bit differential mode 16-bit single-ended mode dnl ? ? ? 2.5 ? 2.5 ? 3 ? 3 lsb 2 t 13-bit differential mode 12-bit single-ended mode ? ? ? 0.7 ? 0.7 ? 1 ? 1 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 0.75 ? 0.75 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t 3 integral non-linearity 16-bit differential mode 16-bit single-ended mode inl ? ? ? 6.0 ? 10.0 ? 12.0 ? 16.0 lsb 2 t 13-bit differential mode 12-bit single-ended mode ? ? ? 1.0 ? 1.0 ? 2.0 ? 2.0 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.5 ? 0.5 ? 1.0 ? 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.3 ? 0.3 ? 0.5 ? 0.5 t 4 zero-scale error 16-bit differential mode 16-bit single-ended mode e zs ? ? ? 4.0 ? 4.0 +16/0 +16/-8 lsb 2 t v adin = v ssa 13-bit differential mode 12-bit single-ended mode ? ? ? 0.7 ? 0.7 ? 2.0 ? 2.0 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.4 ? 0.4 ? 1.0 ? 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 36 5 full-scale error 16-bit differential mode 16-bit single-ended mode e fs ? ? +8/0 +12/0 +24/0 +24/0 lsb 2 t v adin = v dda 13-bit differential mode 12-bit single-ended mode ? ? ? 0.7 ? 0.7 ? 2.0 ? 2.5 t 11-bit differential mode 10-bit single-ended mode ? ? ? 0.4 ? 0.4 ? 1.0 ? 1.0 t 9-bit differential mode 8-bit single-ended mode ? ? ? 0.2 ? 0.2 ? 0.5 ? 0.5 t 6 quantization error 16-bit modes e q ? ?1 to 0 ? lsb 2 d < 13-bit modes ? ? ? 0.5 7 effective number of bits 16-bit differential mode avg=32 avg=16 avg=8 avg=4 avg=1 eno b 14.3 13.8 13.4 13.1 12.4 14.5 14.0 13.7 13.4 12.6 ? ? ? ? ? bits c f in = f sample /10 0 8 signal to noise plus distortion see enob sina d db 9 total harmonic distortion 16-bit differential mode avg=32 thd ? ?95.8 ?90.4 db c f in = f sample /10 0 16-bit single-ended mode avg=32 ? ? ? d 10 spurious free dynamic range 16-bit differential mode avg=32 sfdr 91.0 96.5 ? db c f in = f sample /10 0 16-bit single-ended mode avg=32 ? ? ? d 11 input leakage error all modes e il i in * r as mv d i in = leakage current (refer to dc characteri stics) 1 all accuracy numbers assume the adc is calibrated with v refh =v dda 2 typical values assume v dda = 3.0v, temp = 25 ? c, f adck =2.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3 1 lsb = (v refh ? v refl )/2 n table 17. 16-bit sar adc charac teristics full operating range (v refh = v dda , ? 2.7 v, v refl = v ssa , f adack ? 4 mhz, adhsc = 1) (continued) # characteristic conditions 1 symb min typ 2 max unit c comment sinad 6.02 enob ? 1.76 + = freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 37 3.10 mcg and external oscill ator (xosc) characteristics table 18. mcg (temperature range = ?40 to 105 c ambient) # rating symbol min typical max unit c 1 internal reference startup time t irefst ?55 100 ? sd 2 average internal reference frequency factory trimmed at vdd=3.0 v and temp=25 ?c f int_ft ? 31.25 ? khz c user trimmed 31.25 ? 39.0625 c 3 dco output frequency range ? trimmed low range (drs=00) f dco_t 16 ? 20 mhz c mid range (drs=01) 32 ? 40 c high range 1 (drs=10) 1 this should not exceed the maximum cpu frequency for this device which is 50.33 mhz. 40 ? 60 c 4 resolution of trimmed dco output frequency at fixed voltage and temperature with ftrim ? f dco_res_t ? ?? 0.1 ?? 0.2 %f dco c without ftrim ? ?? 0.2 ?? 0.4 c 5 total deviation of trimmed dco output frequency over voltage and temperature over voltage and temperature ? f dco_t ? ? 1.0 ?? 2 %f dco p over fixed voltage and temp range of 0 ? 70 ?c ? ?? 0.5 ?? 1c 6 acquisition time fll 2 t fll_acquire ?? 1 ms c pll 3 t pll_acquire ?? 1 d 7 long term jitter of dco output clock (averaged over 2ms interval) 4 c jitter ?0.02 0.2 %f dco c 8 vco operating frequency f vco 7.0 ? 55.0 mhz d 9 pll reference frequency range f pll_ref 1.0 ? 2.0 mhz d 10 jitter of pll output clock measured over 625ns 5 long term f pll_jitter_625 ns ? 0.566 4 ? %f pll d 11 lock frequency tolerance entry 6 d lock ?? 1.49 ? ?? 2.98 % d exit 7 d unl ?? 4.47 ? ?? 5.97 d 12 lock time fll t fll_lock ?? t fll_acquire+ 1075(1/ f int_t) s d pll t pll_lock ?? t pll_acquire+ 1075(1/ f pll_re f) d 13 loss of external clock minimum frequency - range = 0 f loc_low (3/5) x f int_t ??khzd 14 loss of external clock minimum frequency - range = 1 f loc_high (16/5) x f int_t ??khzd freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 38 2 this specification applies to any time the fll reference source or reference divide r is changed, trim value is changed, dmx32 b it is changed, drs bit is changed, or changing from fll disabled (b lpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specific ation assumes it is already running. 3 this specification applies to any time the pll vco divider or referenc e divider is changed, or changing from pll disabled (blpe , blpi) to pll enabled (pbe, pee). if a crystal/resonator is being us ed as the reference, this specification assumes it is alread y running. 4 jitter is the average deviation from the programmed frequen cy measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered suppl ies and clocked by a stable exte rnal clock signal. noise injecte d into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 5 625 ns represents 5 time quanta for can appl ications, under worst-case conditions of 8 mhz can bus clock, 1 mbps can bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time bet ween a synchronization edge and th e sample point of a bit using 8 time quanta per bit. 6 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg will not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 7 below d unl minimum, the mcg will not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. table 19. xosc (temperature range = ?40 to 105 c ambient) # characteristic symbol min typ 1 max unit c 1 oscillator crystal or resonator (erefs = 1, erclken = 1) ? low range (range = 0) f lo 32 ? 38.4 khz d ? high range (range = 1), ? fee or fbe mode 2 f hi-fll 1? 5mhzd ? high range (range = 1), ? pee or pbe mode 3 f hi-pll 1? 16mhzd ? high range (range = 1), ? high gain (hgo = 1), ? blpe mode f hi-hgo 1? 16mhzd ? high range (range = 1), ? low power (hgo = 0), ? blpe mode f hi-lp 1? 8mhzd 2 load capacitors c 1 c 2 see crystal or resonator manufacturer?s recommendation. d 3 feedback resistor ? low range (32 khz to 38.4 khz) r f ? 10 ? m ? d ? high range (1 mhz to 16 mhz) ?? 1 ? d 4 series resistor ? low range ? low gain (hgo = 0) r s ?0 ? k? d ? high gain (hgo = 1) ? 100 ? d 5 series resistor ? high range ? low gain (hgo = 0) r s ?0 ? k? d ? high gain (hgo = 1) d ? 8 mhz ? 0 0 d 4 mhz ? 0 10 d 1 mhz ? 0 20 d freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 39 o 3.11 mini-flexbus timing specifications a multi-function external bus inte rface called mini-flexbus is provi ded with basic functionality to interface to slave-only devices up to a maximum bus frequency of 25.1666 mhz . it can be directly connected to asynchronous or synchronous devices such as external boot roms, flash memories , gate-array logic, or other simple target (slave) devices with little or no additional circuitry. for asynchronous devices a simple chip-select based interface can be used. all processor bus timings are synchronous; that is, i nput setup/hold and output de lay are given in respect to the rising edge of a reference clock, mb_clk. the mb_clk frequency is half the internal system bus frequency. the following timing numbers indicate wh en data is latched or driven ont o the external bus, relative to the mini-flexbus output clock (mb_clk) . all other timing relationships can be derived from these values. 6 crystal start-up time 4 ? low range, low gain (range = 0, hgo = 0) t cstl-lp ? 200 ? ms d ? low range, high gain (range = 0, hgo = 1) t cstl-hg o ?400 ? d ? high range, low gain (range = 1, hgo = 0) 5 t csth-lp ?5 ? d ? high range, high gain (range = 1, hgo = 1) 5 t csth-hg o ?15 ? d 1 data in typical column was characterized at 3.0 v, 25 ? c or is typical recommended value. 2 when mcg is configured for fee or fbe mode, input clock source must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. 3 when mcg is configured for pee or pbe mode, input clock source must be divisible using rdiv to within the range of 1 mhz to 2 m hz. 4 this parameter is characterized and not te sted on each device. proper pc board layout porcedures must be followed to achieve sp ecifications. 5 4 mhz crystal. table 19. xosc (temperature range = ?40 to 105 c ambient) (continued) # characteristic symbol min typ 1 max unit c mcu extal xtal r s c 2 crystal or resonator r f c 1 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 40 figure 9. mini-flexbus read timing table 20. mini-flexbus ac timing specifications num c characteristic min max unit notes ? ? frequency of operation ? 25.1666 mhz ? mb1 d clock period 39.73 ? ns ? mb2 d output valid ? 20 ns 1 1 specification is valid for all mb_a[19:0], mb_d[7:0], mb_cs [1:0], mb_oe , mb_r/w , and mb_ale. mb3 d output hold 1.0 ? ns 1 mb4 d input setup 22 ? ns 2 2 specification is valid for all mb_d[7:0]. mb5 d input hold 10 ? ns 2 fb_a[19 : 16 ] fb_clk s0 s1 s2 s3 fb_r/w fb_ale data[7:0] 8-bit non-mux?d bus 16-bit mux?d bus addr[19 :0] addr[31:24] fb_d[7:0] fb_cs n , fb_oe s0 fb_ad[15:0] fb_ad[19:16] data[15:0] addr[19:16] addr[15:0] mb1 mb2 mb5 mb3 mb4 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 41 figure 10. mini-flexbus write timing fb_clk s0 s1 s2 s3 fb_r/w fb_ale fb_oe data[7:0] 8-bit non-mux?d bus 16-bit mux?d bus addr[19 :8] addr[7:0] fb_ad[19 : 8 ] fb_ad[7:0] fb_cs n s0 fb_ad[15:0] data[15:0] fb_ad[19:16] addr[19:16] addr[15:0] mb1 mb2 mb3 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 42 3.12 ac characteristics this section describes ac timing charac teristics for each peripheral system. 3.12.1 control timing table 21. control timing # symbol parameter min typical 1 max c unit 1 f bus bus frequency (t cyc = 1/f bus )m h z v dd ? 1.8 v dc ? 10 d v dd > 2.1 v dc ? 20 d v dd > 2.4 v dc ? 25.165 d 2t lpo internal low-power oscillator period 700 1000 1300 p ? s 3t extrst external reset pulse width 2 (t cyc = 1/f self_reset ) 100 ? ? d ns 4t rstdrv reset low drive 66 x t cyc ??dns 5t mssu active background debug mode latch setup time 500 ? ? d ns 6t msh active background debug mode latch hold time 100 ? ? d ns 7 t ilih, t ihil irq pulse width ? asynchronous path 2 ? synchronous path 3 100 1.5 x t cyc ?? d ns 8 t ilih, t ihil kbipx pulse width ? asynchronous path 2 ? synchronous path 3 100 1.5 x t cyc ?? d ns freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 43 figure 11. reset timing figure 12. irq/kbipx timing 9t rise , t fall port rise and fall time (load = 50 pf) 4 , low drive ns slew rate control disabled (ptxse = 0) ?11?d slew rate control enabled (ptxse = 1) ?35?d slew rate control disabled (ptxse = 0) ?40?d slew rate control enabled (ptxse = 1) ?75?d 1 typical values are based on characterization data at v dd = 5.0 v, 25 ? c unless otherwise stated. 2 this is the shortest pulse that is guaranteed to be reco gnized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. 3 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 ? c to 105 ? c. table 21. control timing (continued) # symbol parameter min typical 1 max c unit t extrst reset pin t ihil irq/kbipx t ilih irq/kbipx freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 44 3.12.2 tpm timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 13. timer external clock figure 14. timer input capture pulse table 22. tpm input timing # c function symbol min max unit 1 ? external clock frequency f tpmext dc f bus /4 mhz 2 ? external clock period t tpmext 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t tpmext t clkh t clkl tpmxclk t icpw tpmxchn t icpw tpmxchn freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 45 3.13 spi characteristics table 23 and figure 15 through figure 18 describe the timing requir ements for the spi system. table 23. spi timing no. 1 1 numbers in this column identify elements in figure 15 through figure 18 . characteristic 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit c 1 operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz hz d 2 spsck period master slave t spsck 2 4 2048 ? t cyc t cyc d 3 enable lead time master slave t lead 1 ? 2 1 ? ? t spsck t cyc d 4 enable lag time master slave t lag 1 ? 2 1 ? ? t spsck t cyc d 5 clock (spsck) high or low time master slave t wspsck t cyc ? ? 30 t cyc ? 30 1024 t cyc ? ns ns d 6 data setup time (inputs) master slave t su t su 15 15 ? ? ns ns d 7 data hold time (inputs) master slave t hi t hi 0 25 ? ? ns ns d 8 slave access time 3 3 time to data active from high-impedance state. t a ?1t cyc d 9 slave miso disable time 4 4 hold time to high-impedance state. t dis ?1t cyc d 10 data valid (after spsck edge) master slave t v ? ? 25 25 ns ns d 11 data hold time (outputs) master slave t ho 0 0 ? ? ns ns d 12 rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns d 13 fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns d freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 46 figure 15. spi master timing (cpha = 0) figure 16. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 2 2 3 5 6 7 11 12 5 11 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit orde r is lsb, bit 1, ..., bit 6, msb. notes: 2 2 3 4 5 6 7 11 12 5 4 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 47 figure 17. spi slave timing (cpha = 0) figure 18. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined, but normally ms b of character just received 2 2 3 4 6 7 8 9 11 12 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined, but normally ls b of character just received 2 2 3 4 6 7 8 9 11 12 4 5 5 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 48 3.14 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information abou t program/erase operations , see the memory chapter in the reference manual for this device (mcf51mm256rm). table 24. flash characteristics # characteristic symbol min typical max unit c 1 supply voltage for program/erase ?40 ? c to 105 ?cv prog/erase 1.8 ? 3.6 v d 2 supply voltage for read operation v read 1.8 ? 3.6 v d 3 internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz d 4 internal fclk period (1/fclk) t fcyc 5 ? 6.67 ? sd 5 byte program time (random location) 2 t prog 9t fcyc p 6 byte program time (burst mode) 2 t burst 4t fcyc p 7 page erase time 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calc ulating approximate time to program and erase. t page 4000 t fcyc p 8 mass erase time 2 t mass 20,000 t fcyc p 9 program/erase endurance 3 t l to t h = ?40 ? c to + 105?c t = 25 ?c 3 typical endurance for flash was evaluated for this product family on the hc9s12dx 64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 ? ? 100,000 ? ? cycles c 10 data retention 4 4 typical data retention values are based on intrinsic capability of the te chnology measured at high temperature and de-rated to 25 ? c using the arrhenius equation. for additional information on how freescale defines typical data rete ntion, please refer to engineering bul letin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 49 3.15 usb electricals the usb electricals for the usb on-the-go modul e conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. if the freescale usb on-the-go implementation has electrical characteristics that deviate from the standard or require additional information, this spa ce would be used to communicate that information. table 25. internal usb 3.3 v voltage regulator characteristics # characteristic symbol min typ max unit c 1 regulator operating voltage v regin 3.9 ? 5.5 v c 2 vreg output v regout 3 3.3 3.75 v p 3 v usb33 input with internal vreg disabled v usb33in 33.33.6vc 4 vreg quiescent current i vrq ?0.5?mac freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 50 3.16 vref electrical specifications table 26. vref electrical specifications # characteristic symbol min max unit c 1 supply voltage v dda 1.80 3.6 v c 2 temperature t a ?40 105 c c 3 output load capacitance c l ? 100 nf d 4 maximum load ? ? 10 ma ? 5 voltage reference output with factory tr i m . v dd = 3 v at 25c. vout 1.145 1.153 vp 6 temperature drift (vmin ? vmax across the full temperature range) tdrift ? 25 mv 1 1 see typical chart that follows ( figure 19 ). t 7 aging coefficient 2 2 linear reliability model (1008 hours stress at 125c = 10 ye ars operating life) used to calculate aging v/year. v refo data recorded per month. ac ? 60 v/year c 8 powered down cu rrent (off mode, vrefen=0, vrsten=0) i ? 0.10 a c 9 bandgap only (mode_lv[1:0] = 00) i ? 75 a t 10 low-power buffer (mode_lv[1:0] = 01) i ? 125 a t 11 tight-regulation buffer (mode_lv[1:0] = 10) i?1 . 1m at 12 load regulation mode_lv = 10 ? ? 100 v/ma c 13 line regulation mode = 1:0, tight regulation v dd < 2.3 v, delta v dda = 100 mv, vrefh = 1.2 v driven externally with vrefo disabled. (power supply rejection) dc 70 ? db c table 27. vref limited range operating behaviors # characteristic symbol min max unit c notes 1 voltage reference output with factory trim (temperature range from 0 c to 50 c) v out 1.149 1.152 mv t 2 temperature drift (v min ? v max temperature range from 0 c to 50 c) t drift ?3m v 1 1 see typical chart that follows ( figure 19 ). t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 51 figure 19. typical vref output vs. temperature figure 20. typical vref output vs. v dd freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 52 3.17 triamp electrical parameters table 28. triamp characteristics 1.8 ? 3.6 v, ? 40c~105c #c h a r a c t e r i s t i c 1 symbol min typ 2 max unit c 1 operating voltage v dd 1.8 ? 3.6 v c 2 supply current (i out =0ma, cl=0) low-power mode i supply ?52 60 ? at 3 supply current (i out =0ma, cl=0) high-speed mode i supply ?432480 ? at 4 input offset voltage v os ? 1 5mvt 5 input offset voltage temperature drift ? vos ?600 ? ? vt 6 input offset current i os ? 120 500 pa t 7 input bias current (0 ~ 50c) i bias ? < 350 < 500 pa t 8 input bias current (?40 ~ 105c) i bias ? 3 6.55 na t 9 input common mode voltage low v cml 0? ? vt 10 input common mode voltage high v cmh ?? v dd ?1.4 vt 11 input resistance r in 500 ? ? m ? t 12 input capacitances c in ?? 5 pfd 13 ac input impedance (f in =100khz) | x in | ?1 ?m ? d 14 input common mode rejection ratio cmrr 60 70 ? db t 15 power supply rejection ration psrr 60 70 ? db t 16 slew rate ( ? v in =100mv) low-power mode sr ? 0.1 ? v/ ? st 17 slew rate ( ? v in =100mv) high-speed mode sr ? 1 ? v/ ? st 18 unity gain bandwidth (low-power mode) 50pf gbw 0.15 0.25 ? mhz t 19 unity gain bandwidth (high-speed mode) 50pf gbw ? 1.6 ? mhz t 20 dc open loop voltage gain a v ?80 ? dbt 21 load capacitance driving capability cl(max) ? ? 100 pf t 22 output impedance ac open loop (@100 khz low-power mode) r out ?1.4 ? k ? d 23 output impedance ac open loop (@100 khz high-speed mode) r out ?184 ? ? d 24 output voltage range triout 0.15 ? v dd ? 0.15 vt 25 output drive capability i out ? 1.0 ? ma t 26 gain margin gm 20 ? ? db d 27 phase margin pm 45 55 ? deg t freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 53 3.18 opamp electrical parameters 28 input voltage noise density f= 1 khz ? 160 ? nv/ ? hz t 1 all parameters are measured at 3.0 v, cl= 47 pf across temperature ? 40 to + 105 c unless specified. 2 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. table 29. opamp characteristics 1.8 ? 3.6 v # characteristics 1 symbol min typ 2 max unit c 1 operating voltage v dd 1.8 ? 3.6 v c 2 supply current (i out =0ma, cl=0 low-power mode) i supply ?4880 ? at 3 supply current (i out =0ma, cl=0 high-speed mode) i supply ? 350 500 ? at 4 input offset voltage v os ? ? 2 ? 6mvt 5 input offset voltage temperature coefficient ? vos ?10? ? v/c t 6 input offset current (?40c to 105c) i os ? ? 2.5 ? 250 na t 7 input offset current (?40c to 50c) i os ??45nat 8 positive input bias current (?40c to 105c) i bias ?0.83.5nat 9 positive input bias current (?40c to 50c) i bias ?? ? 2nat 10 negative input bias current (?40c to 105c) i bias ? 2.5 250 na t 11 negative input bias current (?40c to 50c) i bias ??45nat 12 input common mode voltage low v cml 0.1 ? ? v t 13 input common mode voltage high v cmh ??v dd vt 14 input resistance r in ? 500 ? m ? t 15 input capacitances c in ??10pfd 16 ac input impedance (f in =100khz negative channel) | x in | ?52?k ? d 17 ac input impedance (f in =100khz positive channel) | x in | ? 132 ? k ? d 18 input common mode rejection ratio cmrr 55 65 ? db t 19 power supply rejection ratio psrr 60 65 ? db t 20 slew rate ( ? v in =100mv low-power mode) sr 0.1 ? ? v/ ? st 21 slew rate ( ? v in =100mv high-speed mode) sr 1 ? ? v/ ? st 22 unity gain bandwidth (low-power mode) gbw 0.2 ? ? mhz t 23 unity gain bandwidth (high-speed mode) gbw 1 ? ? mhz t 24 dc open loop voltage gain a v 80 90 ? db t 25 load capacitance driving capability cl(max) ? ? 100 pf t 26 output impedance ac open loop (@100 khz low-power mode) r out ?4k? ? d table 28. triamp characteristics 1.8 ? 3.6 v, ? 40c~105c (continued) #c h a r a c t e r i s t i c 1 symbol min typ 2 max unit c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
electrical characteristics freescale semiconductor 54 27 output impedance ac open loop (@100 khz high-speed mode) r out ? 220 ? ? d 28 output voltage range v out 0.15 ? v dd ?0.1 5 vt 29 output drive capability i out ? 0.5 ? 1.0 ? ma t 30 gain margin gm 20 ? ? db d 31 phase margin pm 45 55 ? deg t 32 gpamp startup time (low-power mode) (tolerance < 1%, vin = 0.5 vp?p, cl = 25 pf, rl = 100k) t startup ?4?ust 33 gpamp startup time (low-power mode) (tolerance < 1%, vin = 0.5 vp?p, cl = 25 pf, rl = 100k) t startup ?1?ust 34 input voltage noise density f=1 khz ? 250 ? nv/ ? hz t 1 all parameters are measured at 3.3 v, cl =4 7 pf across temperature ? 40 to + 105c unless specified. 2 data in typical column was characterized at 3.0 v, 25c or is typical recommended value. table 29. opamp characteristics 1.8 ? 3.6 v (continued) # characteristics 1 symbol min typ 2 max unit c freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
ordering information freescale semiconductor 55 4 ordering information this section contains ordering informat ion for the device numbering system. see table 2 for feature summary by package information. 4.1 part numbers 4.2 package information table 30. orderable part number summary freescale part number description flash / sram (kbytes) package temperature mcf51mm256vml mcf51mm256 coldfire microcontroller 256k/32k 104 mapbga ?40 to 105 c mcf51mm256vll mcf51mm256 coldfire microcontroller 256k/32k 100 lqfp ?40 to 105 c mcf51mm256vmb mcf51mm256 coldfire microc ontroller 256k/32k 81 mapbga ?40 to 105 c mcf51mm256vlk mcf51mm256 coldfire microcontroller 256k/32k 80 lqfp ?40 to 105 c MCF51MM128VMB mcf51mm128 coldfire microc ontroller 128k/32k 81 mapbga ?40 to 105 c mcf51mm128vlk mcf51mm128 coldfire microcontroller 128k/32k 80 lqfp ?40 to 105 c mcf51mm256cml mcf51mm256 coldfire microcontroller 256k/32k 104 mapbga ?40 to 85 c mcf51mm256cll mcf51mm256 coldfire microcontroller 256k/32k 100 lqfp ?40 to 85 c mcf51mm256cmb mcf51mm256 coldfire microcontroller 256k/32k 81 mapbga ?40 to 85 c mcf51mm256clk mcf51mm256 coldfire microcontroller 256k/32k 80 lqfp ?40 to 85 c mcf51mm128cmb mcf51mm128 coldfire microcontroller 128k/32k 81 mapbga ?40 to 85 c mcf51mm128clk mcf51mm128 coldfire microcontroller 128k/32k 80 lqfp ?40 to 85 c table 31. package descriptions pin count package type abbreviation designator case no. document no. 100 low quad flat package lqfp ll 983-03 98ass23308w 80 low quad flat package lqfp lk 1418 98ass23174w 104 mapbga package mapbga ml 1285-02 98arh98267a 81 mapbga package mapbga mb 1662-01 98asa10670d freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
revision history freescale semiconductor 56 4.3 mechanical drawings table 31 provides the available package types and their document numbers. the latest package outline/mechanical drawings are available on the mcf51mm256/128 product summary pages at http://www.freescale.com . to view the latest drawing, either: ? click on the appropriate link in table 31, or ? open a browser to the freescale ? website ( http://www.freescale.com ), and enter the appropriate document number (from table 31 ) in the ?enter keyword? search box at the top of the page. 5 revision history this section lists major changes between versions of the mcf51mm256 data sheet. table 32. revision history revision date description 0 march/april 2009 initial draft 1 july 2009 ? revised to follow standard template. ? removed extraneous headings from the toc. ? corrected units for monotoncity to be blank in for the dac specification. ? updated adc characteristic tables to include 16-bit sar in headings. 2 july 2009 ? changed mcg (xosc) electricals table - row 2, average internal reference frequency typical value from 32.768 to 31.25. 3 april 2010 ? updated thermal characteristics table. reinserted the 81 and 104 mapbga devices. ? revised the esd and latch-up protection characeristic description to read: latch-up current at t a = 125c. ? changed table . dc characteristics rows 2 and 4, to 1.8 v, iload = -600 ma conditions to 1.8 v, iload = 600 ? a respectively. ? corrected the 16-bit sar adc operating condition table ref voltage high min value to be 1.13 instead of 1.15. ? updated the adc electricals. ? inserted the mini-flexbus timing specifications. ? added a temp drift parameter to t he vref electrical specifications. ? removed the s08 naming convention diagram. ? updated the orderable part number summary to include the freescale part number suffixes. ? completed the package description table values. ? changed the 80lqfp package drawing from 98arl10530d to 98ass23174w. updated electrical characteristic data. 4 october 2010 ? updated with the latest characteristic data. added several figures. added the adc typical operation table. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
mcf51mm256 rev. 4, 10/2010 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center http://compass.freescale.net/go/168063291 1-800-441-2447 or 1-303-675-2140 fax: 1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009-2010. all rights reserved. freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

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